This invention relates to semiconductors, and more particularly to transistors for use in memories.
As transistor geometries have dramatically been reduced to sub-micron dimensions, transistor structures have been forced to be altered due to the impact on the device physics that the smaller dimensions have created. In particular, the channel of a transistor has become extremely narrow. Due to the small length of the channel, the drain electrode of a transistor begins to negatively control the current conduction within the channel rather than the gate electrode being the controlling mechanism. This problem is well documented and is commonly referred to as a short channel effect. To reduce the problem of short channel effect, others have proposed a transistor structure wherein a gate electrode is positioned on opposite sides of the channel. While this approach dramatically reduces the short channel effect problem, the ability to mass manufacture such a structure is problematic because properly aligning the oppositely positioned gates is very difficult to implement for mass production. As an alternative, a transistor structure having a vertical silicon channel that is surrounded by the gate electrode has been proposed to reduce short channel effects. Such transistors are referred to by several different names including FINFETs and double-gated transistors. While some implementations of FINFET transistors have a single gate electrode, other implementations have used two electrically isolated gate electrodes for improved performance including control of the transistor""s threshold voltage. In order to electrically isolate the two gate electrodes that are around the channel, a chemical mechanical polish (CMP) or polishing step has been used. Due to the narrow fin structure of these transistors, the polishing step tends to cause uneven polishing or xe2x80x9cdishingxe2x80x9d of the transistor device.
Reduced transistor structures have also brought about the ability to integrate both non-volatile (e.g. read-only-memory and Flash) and volatile (DRAM and SRAM) memory arrays for system on chip (SOC) applications. Typically different transistor structures implemented with differing processes are required to implement both non-volatile and volatile memory arrays. For example, a Flash memory transistor is implemented with a floating gate structure that is between a channel and a control gate. In contrast, a DRAM memory transistor is implemented with a planar transistor controlling a deep trench capacitor. The planar transistor uses a single plane channel that separates a source and a drain and that is controlled by an overlying gate. The requirement to implement both volatile and non-volatile memory arrays on a single integrated circuit therefore adds significant cost since differing processes and structures must be implemented. Additionally, due to the different transistor structures that are required, the operating characteristics of the transistors on a same integrated circuit may significantly differ.